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preliminary this is a product that has fixed target specifications but are subject ramtron international corporation to change pending characterization results. 1850 ramtron drive, colorado springs, co 80921 (800) 545-fram, (719) 481-7000 rev. 1.2 http://www.ramtron.com may 2010 page 1 of 13 fm28v100 1mbit bytewide f-ram memory features 1mbit ferroelectric nonvolatile ram ? organized as 128kx8 ? high endurance 100 trillion (10 14 ) read/writes ? nodelay? writes ? page mode operation to 33mhz ? advanced high-reliability ferroelectric process superior to battery-backed sram modules ? no battery concerns ? monolithic reliability ? true surface mount solution, no rework steps ? superior for moisture, shock, and vibration sram replacement ? jedec 128kx8 sram pinout ? 60 ns access time, 90 ns cycle time low power operation ? 2.0v ? 3.6v power supply ? standby current 90 a (typ) ? active current 7 ma (typ) industry standard configurations ? industrial temperature -40 c to +85 c ? 32-pin ?green?/rohs package general description the fm28v100 is a 128k x 8 nonvolatile memory that reads and writes like a standard sram. a ferroelectric random access memory or f-ram is nonvolatile, which means that data is retained after power is removed. it provides data retention for over 10 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed sram (bbsram). fast write timing and very high write endurance make f-ram superior to other types of memory. in-system operation of the fm28v100 is very similar to other ram devices and can be used as a drop-in replacement for standard sram. read and write cycles may be triggered by toggling a chip enable pin or simply by changing the address. the f-ram memory is nonvolatile due to its unique ferroelectric memory process. these features make the fm28v100 ideal for nonvolatile memory applications requiring frequent or rapid writes in the form of an sram. device specifications are guaranteed over the industrial temperature range -40c to +85c. pin configuration * reserved for a17 on 2mb ordering information fm28v100-tg 32-pin ?green?/rohs tsop FM28V100-TGTR 32-pin ?green?/rohs tsop, tape & reel tsop-i 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a11 a9 a8 a13 we ce2 a15 vdd nc* a16 a14 a12 a7 a6 a5 a4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 oe a10 ce1 dq7 dq6 dq5 dq4 dq3 vss dq2 dq1 dq0 a0 a1 a2 a3
fm28v100 - 128kx8 fram rev. 1.2 may 2010 page 2 of 13 figure 1. block diagram pin descriptions pin name type pin description a(16:0) input address inputs: the 17 address lines select one of 131,072 bytes in the f-ram array. the address value is latched on the falling edge of /ce1 (while ce2 high) or the rising edge of ce2 (while /ce1 low). addresses a(2:0) are used for page mode read and write operations. /ce1, ce2 input chip enable inputs: the device is selected and a new memory access begins on the falling edge of /ce1 (while ce2 high) or the rising edge of ce2 (while /ce1 low). the entire address is latched internally at this point. the ce2 pin is pulled up internally. /we input write enable: a write cycle begins when /we is asserted. the rising edge causes the fm28v100 to write the data on the dq bus to the f-ram array. the falling edge of /we latches a new column address for fast page mode write cycles. /oe input output enable: when /oe is low, the fm28v100 drives the data bus when valid data is available. deasserting /oe high tri-states the dq pins. dq(7:0) i/o data: 8-bit bi-directional data bus for accessing the f-ram array. nc - no connect: this pin has no internal connection. vdd supply supply voltage vss supply ground control logic we a (16:3) a (2:0) i/o latch & bus drive r oe dq(7:0) a (16:0) column decode r . . . address latch row decoder ce1, ce2 2 16k x 64 f-ram array
fm28v100 - 128kx8 fram rev. 1.2 may 2010 page 3 of 13 functional truth table 1 /ce1 ce2 /we a(16:3) a(2:0) operation h x x l x x x x x x standby/idle l h h h v v v v read l h h no change change page mode read l h h change v random read l h l l v v v v /ce-controlled write 2 l h v v /we-controlled write 2, 3 l h no change v page mode write 4 l h x x x x x x starts precharge notes: 1) h=logic high, l=logic low, v=valid address, x=don?t care. 2) for write cycles, data-in is latched on the rising edge of /ce1 or /we of the falling edge of ce2, whichever comes first. 3) /we-controlled write cycle begins as a read cycle and a(16:3) is latched then. 4) addresses a(2:0) must remain stable for at least 15 ns during page mode operation.
fm28v100 - 128kx8 fram rev. 1.2 may 2010 page 4 of 13 overview the fm28v100 is a bytewide f-ram memory logically organized as 131,072 x 8 and is accessed using an industry standard parallel interface. all data written to the part is immediately nonvolatile with no delay. the device offers page mode operation which provides higher speed access to addresses within a page (row). an access to a different page is triggered by toggling a chip enable pin or simply by changing the upper address a(16:3). memory operation users access 131,072 memory locations with 8 data bits each through a parallel interface. the f-ram array is organized as 16,384 rows and each row has 8 column locations (bytes), which allows fast access in page mode operation. once an initial address has been latched by the falling edge of /ce1 (while ce2 high) or the rising edge of ce2 (while /ce1 low), subsequent column locations may be accessed without the need to toggle a chip enable. when either chip enable pin is deasserted, a precharge operation begins. writes occur immediately at the end of the access with no delay. the /we pin must be toggled for each write operation. read operation a read operation begins on the falling edge of /ce1 (while ce2 high) or the rising edge of ce2 (while /ce1 low). the /ce-initiated access causes the address to be latched and starts a memory read cycle if /we is high. data becomes available on the bus after the access time has been satisfied. once the address has been latched and the access completed, a new access to a random location (different row) may begin while both chip enables are still active. the minimum cycle time for random addresses is t rc . note that unlike srams, the fm28v100?s /ce- initiated access time is faster than the address cycle time. the fm28v100 will drive the data bus only when /oe is asserted low and the memory access time has been satisfied. if /oe is asserted prior to completion of the memory access, the data bus will not be driven until valid data is available. this feature minimizes supply current in the system by eliminating transients caused by invalid data being driven onto the bus. when /oe is inactive, the data bus will remain hi-z. write operation writes occur in the fm28v100 in the same time interval as reads. the fm28v100 supports both /ce- and /we-controlled write cycles. in both cases, the address is latched on the falling edge of /ce1 (while ce2 high) or the rising edge of ce2 (while /ce1 low). in a /ce-controlled write, the /we signal is asserted prior to beginning the memory cycle. that is, /we is low when the device is activated with a chip enable. in this case, the device begins the memory cycle as a write. the fm28v100 will not drive the data bus regardless of the state of /oe as long as /we is low. input data must be valid when the device is deselected with a chip enable. in a /we-controlled write, the memory cycle begins when the device is activated with a chip enable. the /we signal falls some time later. therefore, the memory cycle begins as a read. the data bus will be driven if /oe is low, however it will hi-z once /we is asserted low. the /ce- and /we-controlled write timing cases are shown on page 12. in the write cycle timing 2 diagram, the data bus is shown as a hi-z condition while the chip is write-enabled and before the required setup time. although this is drawn to look like a mid-level voltage, it is recommended that all dq pins comply with the minimum v ih /v il operating levels. write access to the array begins on the falling edge of /we after the memory cycle is initiated. the write access terminates on the deassertion of /we, /ce1, or ce2, whichever comes first. a valid write operation requires the user to meet the access time specification prior to deasserting /we, /ce1, or ce2. data setup time indicates the interval during which data cannot change prior to the end of the write access. unlike other truly nonvolatile memory technologies, there is no write delay with f-ram. since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. the entire memory operation occurs in a single bus cycle. data polling, a technique used with eeproms to determine if a write is complete, is unnecessary. page mode operation the fm28v100 provides the user fast access to any data within a row element. each row has eight column locations (bytes). an access can start anywhere within a row and other column locations may be accessed without the need to toggle the ce pins. for page mode reads, once the first data byte is driven onto the bus, the column address inputs a(2:0) may be changed to a new value. a new data byte is then driven to the dq pins. for page mode writes, the first write pulse defines the first write access. while the device is selected (both chip enables asserted), a subsequent write pulse along with a new column address provides a page mode write access.
fm28v100 - 128kx8 fram rev. 1.2 may 2010 page 5 of 13 precharge operation the precharge operation is an internal condition in which the state of the memory is prepared for a new access. precharge is user-initiated by driving at least one of the chip enable signals to an inactive state. the chip enable must remain inactive for at least the minimum precharge time t pc . precharge is also activated by changing the upper addess a(16:3). the current row is first closed prior to accessing the new row. the device automatically detects an upper order address change which starts a precharge operation, the new address is latched, and the new read data is valid within the t aa address access time. refer to the read cycle timing 1 diagram on page 9. likewise a similar sequence occurs for write cycles. refer to the write cycle timing 3 diagram on page 11. the rate at which random addresses can be issued is t rc and t wc , respectively. endurance the fm28v100 is capable of being accessed at least 10 14 times ? reads or writes. an f-ram memory operates with a read and restore mechanism. therefore, an endurance cycle is applied on a row basis. the f-ram architecture is based on an array of rows and columns. rows are defined by a16-a3 and column addresses by a2-a0. the array is organized as 16k rows of 8-bytes each. the entire row is internally accessed once whether a single byte or all eight bytes are read or written. each byte in the row is counted only once in an endurance calculation. the user may choose to write cpu instructions and run them from a certain address space. the table below shows endurance calculations for 256-byte repeating loop, which includes a starting address, 7 page mode accesses, and a ce precharge. the number of bus clocks needed to complete an 8-byte transaction is 8+1 at lower bus speeds, but 9+2 at 33mhz due to initial read latency and an extra clock to satisfy the device?s precharge timing constraint t pc . the entire loop causes each byte to experience only one endurance cycle. f-ram read and write endurance is virtually unlimited even at 33mhz system bus clock rate. table 1. time to reach 100 trillion cycles for repeating 256-byte loop bus freq (mhz) bus cycle time (ns) 256-byte transaction time ( s) endurance cycles/sec. endurance cycles/year years to reach 10 14 cycles 33 30 10.56 94,690 2.98 x 10 12 33.5 25 40 12.8 78,125 2.46 x 10 12 40.6 10 100 28.8 34,720 1.09 x 10 12 91.7 5 200 57.6 17,360 5.47 x 10 11 182.8
fm28v100 - 128kx8 fram rev. 1.2 may 2010 page 6 of 13 sram drop-in replacement the fm28v100 has been designed to be a drop-in replacement for standard asynchronous srams. the device does not require the ce pins to toggle for each new address. both ce pins may remain active indefinitely while v dd is applied. when both ce pins are active, the device automatically detects address changes and a new access begins. it also allows page mode operation at speeds up to 33mhz. a typical application is shown in figure 3. it shows a pullup resistor on /ce1 which will keep the pin high during power cycles assuming the mcu/mpu pin tri- states during the reset condition. the pullup resistor value should be chosen to ensure the /ce1 pin tracks v dd yet a high enough value that the current drawn when /ce1 is low is not an issue. although not required, it is recommended that ce2 be tied to v dd if the controller provides an active-low chip enable. figure 3. typical application using pullup resistor on /ce1 for applications that require the lowest power consumption, the ce signals should be active only during memory accesses. due to the external pullup resistor, some supply current will be drawn while /ce1 is low. when /ce1 is high, the device draws no more than the maximum standby current i sb . note that if /ce1 is grounded and ce2 tied to v dd , the user must be sure /we is not low at powerup or powerdown events. if the chip is enabled and /we is low during power cycles, data corruption will occur. figure 4 shows a pullup resistor on /we which will keep the pin high during power cycles assuming the mcu/mpu pin tri-states during the reset condition. the pullup resistor value should be chosen to ensure the /we pin tracks v dd yet a high enough value that the current drawn when /we is low is not an issue. a 10kohm resistor draws 330ua when /we is low and v dd =3.3v. figure 4. use of pullup resistor on /we the fm28v100 is backward compatible with the 1mbit fm20l08 and 256kbit fm18l08 devices. pcb layout recommendations a 0.1uf decoupling capacitor should be placed close to pin 8 (v dd ) and the ground side of the capacitor should be connected to either a ground plane or low impedance path back to pin 24 (v ss ). it is best to use a chip capacitor that has low esr and has good high frequency characteristics. if the controller drives the address and chip enable from the same timing edge, it is best to keep the address routes short and of equal length. a simple rc circuit may be inserted in the chip enable path to provide some delay and timing margin for the fm28v100?s address setup time t as . as a general rule, the layout designer may need to add series termination resistors to controller outputs that have fast transitions or routes that are > 15cm in length. this is only necessary if the edge rate is less than or equal to the round trip trace delay. signal overshoot and ringback may be large enough to cause erratic device behavior. it is best to add a 50 ohm resistor (30 ? 60 ohms) near the output driver (controller) to reduce such transmission line effects. ce2 ce1 we oe a(16:0) dq(7:0) fm28v100 v dd mcu/ mpu r ce2 ce1 we oe a(16:0) dq(7:0) fm28v100 v dd mcu/ mpu r
fm28v100 - 128kx8 fram rev. 1.2 may 2010 page 7 of 13 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss -1.0v to +4.5v v in voltage on any signal pin with respect to v ss -1.0v to +4.5v and v in < v dd +1v t stg storage temperature -55 c to +125 c t lead lead temperature (soldering, 10 seconds) 260 c v esd electrostatic discharge voltage - human body model (aec-q100-002 rev. e) - charged device model (aec-q100-011 rev. b) - machine model (aec-q100-003 rev. e ) 2kv 1.25kv 200v package moisture sensitivity level msl-3 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliabilit y. dc operating conditions (t a = -40 c to +85 c, v dd = 2.0v to 3.6v unless otherwise specified) symbol parameter min typ max units notes v dd power supply 2.0 3.3 3.6 v i dd v dd supply current 7 12 ma 1 i sb standby current ? cmos 90 150 a 2 i li input leakage current 1 a 3 i lo output leakage current 1 a 3 v ih input high voltage 0.7 v dd v dd + 0.3 v v il input low voltage -0.3 0.3 v dd v v oh1 output high voltage ( i oh = -1 ma, v dd =2.7v) 2.4 v v oh2 output high voltage ( i oh = -100 a) v dd -0.2 v v ol1 output low voltage ( i ol = 2 ma, v dd =2.7v) 0.4 v v ol2 output low voltage ( i ol = 150 a) 0.2 v r in address input resistance (ce2) for v in = v ih (min) for v in = v il (max) 40 1 k ? m ? 4 notes 1. v dd = 3.6v, ce cycling at minimum cycle time. all inputs at cmos levels (0.2v or v dd -0.2v), all dq pins unloaded. 2. v dd = 3.6v, /ce1 at v dd or ce2 at v ss , and all other pins at cmos levels (0.2v or v dd -0.2v). 3. v in , v out between v dd and v ss . 4. the input pull-up circuit is stronger (>40k ? ) when the input voltage is above v ih and weak (>1m ? ) when the input voltage is below v il .
fm28v100 - 128kx8 fram rev. 1.2 may 2010 page 8 of 13 read cycle ac parameters (t a = -40 c to +85 c, c l = 30 pf, unless otherwise specified) v dd 2.0 to 2.7v v dd 2.7 to 3.6v symbol parameter min max min max units notes t rc read cycle time 105 - 90 - ns t ce chip enable access time - 70 - 60 ns t a a address access time - 105 - 90 ns t oh output hold time 20 - 20 - ns t aap page mode address access time - 40 - 30 ns t ohp page mode output hold time 3 - 3 - ns t c a chip enable active time 70 - 60 - ns t pc precharge time 35 - 30 - ns t as address setup time (to /ce1, ce2 active) 0 - 0 - ns t ah address hold time (/ce-controlled) 70 - 60 - ns t oe output enable access time - 25 - 15 ns t hz chip enable to output high-z - 10 - 10 ns 1 t ohz output enable high to output high-z - 10 - 10 ns 1 write cycle ac parameters (t a = -40 c to +85 c, unless otherwise specified) v dd 2.0 to 2.7v v dd 2.7 to 3.6v symbol parameter min max min max units notes t wc write cycle time 105 - 90 - ns t c a chip enable active time 70 - 60 - ns t cw chip enable to write enable high 70 - 60 - ns t pc precharge time 35 - 30 - ns t pwc page mode write enable cycle time 40 - 30 - ns t wp write enable pulse width 22 - 18 - ns t as address setup time (to /ce1, ce2 active) 0 - 0 - ns t ah address hold time (/ce-controlled) 70 - 60 - ns t asp page mode address setup time (to /we low) 8 - 5 - ns t ahp page mode address hold time (to /we low) 20 - 15 - ns t wlc write enable low to chip disabled 30 - 25 - ns t wl a write enable low to a(16:3) change 30 - 25 - ns t awh a(16:3) change to write enable high 105 - 90 - ns t ds data input setup time 20 - 15 - ns t dh data input hold time 0 - 0 - ns t wz write enable low to output high z - 10 - 10 ns 1 t wx write enable high to output driven 5 - 5 - ns 1 t ws write enable to ce-active setup time 0 - 0 - ns 1,2 t wh write enable to ce-inactive hold time 0 - 0 - ns 1,2 notes 1 this parameter is characterized but not 100% tested. 2 the relationship between ce?s and /we determines if a /ce- or /we-controlled write occurs. power cycle timing (t a = -40 c to +85 c, v dd = 2.0v to 3.6v unless otherwise specified) symbol parameter min max units notes t vr v dd rise time 50 - s/v 1 t vf v dd fall time 100 - s/v 1 t pu power up (v dd min) to first access time 250 - s t pd last access to power down (v dd min) 0 - s notes 1 slope measured at any point on v dd waveform.
fm28v100 - 128kx8 fram rev. 1.2 may 2010 page 9 of 13 data retention (t a = -40 c to + 85 c) parameter min max units notes data retention 10 - years capacitance (t a = 25 c , f=1 mhz, v dd = 3.3v) symbol parameter min max units notes c i/o input/output capacitance (dq) - 8 pf 1 c in input capacitance - 6 pf 1 notes 1. this parameter is characterized and not 100% tested. ac test conditions input pulse levels 0 to 3v input rise and fall times 3 ns input and output timing levels 1.5v output load capacitance 30 pf read cycle timing 1 (/ce1 low, ce2 high, /oe low) a(16:0) dq(7:0) t rc t oh t aa t oh read cycle timing 2 (/ce-controlled) ce2 a(16:0) oe dq(7:0) t as t ce t ca t pc t oe t ohz t hz t ah ce1
fm28v100 - 128kx8 fram rev. 1.2 may 2010 page 10 of 13 page mode read cycle timing although sequential column addressing is shown, it is not required. write cycle timing 1 (/we-controlled) note: /oe is low only to show effect of /we on dq pins d in ce1 a(16:0) we t ca t pc dq(7:0) t wp t cw t as d out d out t ds t dh t wx t wz t hz t wlc ce2 write cycle timing 2 (/ce-controlled) note: see write operation section for detailed description (page 4).
fm28v100 - 128kx8 fram rev. 1.2 may 2010 page 11 of 13 write cycle timing 3 (/ce1 low, ce2 high) note: /oe is low only to show effect of /we on dq pins page mode write cycle timing although sequential column addressing is shown, it is not required. power cycle timing v dd t vf v dd min min v dd t vr t pu t pd access allowed
fm28v100 - 128kx8 fram rev. 1.2 may 2010 page 12 of 13 mechanical drawing 32-pin shrunk tsop-i (8.0 x 13.4 mm) all dimensions in millimeters tsop package marking scheme legend: xxxxxx= part number, p= package/option (t=tsop ?green?) r=rev code, yy=year, ww=work week, lllllll= lot code example: fm28v100, ?green?/rohs tsop-i package, rev. a, year 2010, work week 18, lot 9482296 ramtron fm28v100-tg a9482296tg 1018 ramtron xxxxxxx-p rlllllll yyww
fm28v100 - 128kx8 fram rev. 1.2 may 2010 page 13 of 13 revision history revision date summary 1.0 10/10/2008 initial release. 1.1 3/25/2009 added tape & reel ordering information. added esd ratings. removed software write protect feature. 1.2 5/25/2010 changed msl package rating. expanded explanation of precharge operation. updated lead temperature rating in abs max table. changed package marking scheme.

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